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3.17.40 SPARC Options

These ‘-m’ options are supported on the SPARC:

-mno-app-regs
-mapp-regs

Specify ‘-mapp-regs’ to generate output using the global registers 2 through 4, which the SPARC SVR4 ABI reserves for applications. This is the default.

To be fully SVR4 ABI-compliant at the cost of some performance loss, specify ‘-mno-app-regs’. You should compile libraries and system software with this option.

-mflat
-mno-flat

With ‘-mflat’, the compiler does not generate save/restore instructions and uses a “flat” or single register window model. This model is compatible with the regular register window model. The local registers and the input registers (0–5) are still treated as “call-saved” registers and are saved on the stack as needed.

With ‘-mno-flat’ (the default), the compiler generates save/restore instructions (except for leaf functions). This is the normal operating mode.

-mfpu
-mhard-float

Generate output containing floating-point instructions. This is the default.

-mno-fpu
-msoft-float

Generate output containing library calls for floating point. Warning: the requisite libraries are not available for all SPARC targets. Normally the facilities of the machine’s usual C compiler are used, but this cannot be done directly in cross-compilation. You must make your own arrangements to provide suitable library functions for cross-compilation. The embedded targets ‘sparc-*-aout’ and ‘sparclite-*-*’ do provide software floating-point support.

-msoft-float’ changes the calling convention in the output file; therefore, it is only useful if you compile all of a program with this option. In particular, you need to compile ‘libgcc.a’, the library that comes with GCC, with ‘-msoft-float’ in order for this to work.

-mhard-quad-float

Generate output containing quad-word (long double) floating-point instructions.

-msoft-quad-float

Generate output containing library calls for quad-word (long double) floating-point instructions. The functions called are those specified in the SPARC ABI. This is the default.

As of this writing, there are no SPARC implementations that have hardware support for the quad-word floating-point instructions. They all invoke a trap handler for one of these instructions, and then the trap handler emulates the effect of the instruction. Because of the trap handler overhead, this is much slower than calling the ABI library routines. Thus the ‘-msoft-quad-float’ option is the default.

-mno-unaligned-doubles
-munaligned-doubles

Assume that doubles have 8-byte alignment. This is the default.

With ‘-munaligned-doubles’, GCC assumes that doubles have 8-byte alignment only if they are contained in another type, or if they have an absolute address. Otherwise, it assumes they have 4-byte alignment. Specifying this option avoids some rare compatibility problems with code generated by other compilers. It is not the default because it results in a performance loss, especially for floating-point code.

-mno-faster-structs
-mfaster-structs

With ‘-mfaster-structs’, the compiler assumes that structures should have 8-byte alignment. This enables the use of pairs of ldd and std instructions for copies in structure assignment, in place of twice as many ld and st pairs. However, the use of this changed alignment directly violates the SPARC ABI. Thus, it’s intended only for use on targets where the developer acknowledges that their resulting code is not directly in line with the rules of the ABI.

-mcpu=cpu_type

Set the instruction set, register set, and instruction scheduling parameters for machine type cpu_type. Supported values for cpu_type are ‘v7’, ‘cypress’, ‘v8’, ‘supersparc’, ‘hypersparc’, ‘leon’, ‘sparclite’, ‘f930’, ‘f934’, ‘sparclite86x’, ‘sparclet’, ‘tsc701’, ‘v9’, ‘ultrasparc’, ‘ultrasparc3’, ‘niagara’, ‘niagara2’, ‘niagara3’, and ‘niagara4’.

Native Solaris and GNU/Linux toolchains also support the value ‘native’, which selects the best architecture option for the host processor. ‘-mcpu=native’ has no effect if GCC does not recognize the processor.

Default instruction scheduling parameters are used for values that select an architecture and not an implementation. These are ‘v7’, ‘v8’, ‘sparclite’, ‘sparclet’, ‘v9’.

Here is a list of each supported architecture and their supported implementations.

v7

cypress

v8

supersparc, hypersparc, leon

sparclite

f930, f934, sparclite86x

sparclet

tsc701

v9

ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4

By default (unless configured otherwise), GCC generates code for the V7 variant of the SPARC architecture. With ‘-mcpu=cypress’, the compiler additionally optimizes it for the Cypress CY7C602 chip, as used in the SPARCStation/SPARCServer 3xx series. This is also appropriate for the older SPARCStation 1, 2, IPX etc.

With ‘-mcpu=v8’, GCC generates code for the V8 variant of the SPARC architecture. The only difference from V7 code is that the compiler emits the integer multiply and integer divide instructions which exist in SPARC-V8 but not in SPARC-V7. With ‘-mcpu=supersparc’, the compiler additionally optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and 2000 series.

With ‘-mcpu=sparclite’, GCC generates code for the SPARClite variant of the SPARC architecture. This adds the integer multiply, integer divide step and scan (ffs) instructions which exist in SPARClite but not in SPARC-V7. With ‘-mcpu=f930’, the compiler additionally optimizes it for the Fujitsu MB86930 chip, which is the original SPARClite, with no FPU. With ‘-mcpu=f934’, the compiler additionally optimizes it for the Fujitsu MB86934 chip, which is the more recent SPARClite with FPU.

With ‘-mcpu=sparclet’, GCC generates code for the SPARClet variant of the SPARC architecture. This adds the integer multiply, multiply/accumulate, integer divide step and scan (ffs) instructions which exist in SPARClet but not in SPARC-V7. With ‘-mcpu=tsc701’, the compiler additionally optimizes it for the TEMIC SPARClet chip.

With ‘-mcpu=v9’, GCC generates code for the V9 variant of the SPARC architecture. This adds 64-bit integer and floating-point move instructions, 3 additional floating-point condition code registers and conditional move instructions. With ‘-mcpu=ultrasparc’, the compiler additionally optimizes it for the Sun UltraSPARC I/II/IIi chips. With ‘-mcpu=ultrasparc3’, the compiler additionally optimizes it for the Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With ‘-mcpu=niagara’, the compiler additionally optimizes it for Sun UltraSPARC T1 chips. With ‘-mcpu=niagara2’, the compiler additionally optimizes it for Sun UltraSPARC T2 chips. With ‘-mcpu=niagara3’, the compiler additionally optimizes it for Sun UltraSPARC T3 chips. With ‘-mcpu=niagara4’, the compiler additionally optimizes it for Sun UltraSPARC T4 chips.

-mtune=cpu_type

Set the instruction scheduling parameters for machine type cpu_type, but do not set the instruction set or register set that the option ‘-mcpu=cpu_type’ does.

The same values for ‘-mcpu=cpu_type’ can be used for ‘-mtune=cpu_type’, but the only useful values are those that select a particular CPU implementation. Those are ‘cypress’, ‘supersparc’, ‘hypersparc’, ‘leon’, ‘f930’, ‘f934’, ‘sparclite86x’, ‘tsc701’, ‘ultrasparc’, ‘ultrasparc3’, ‘niagara’, ‘niagara2’, ‘niagara3’ and ‘niagara4’. With native Solaris and GNU/Linux toolchains, ‘native’ can also be used.

-mv8plus
-mno-v8plus

With ‘-mv8plus’, GCC generates code for the SPARC-V8+ ABI. The difference from the V8 ABI is that the global and out registers are considered 64 bits wide. This is enabled by default on Solaris in 32-bit mode for all SPARC-V9 processors.

-mvis
-mno-vis

With ‘-mvis’, GCC generates code that takes advantage of the UltraSPARC Visual Instruction Set extensions. The default is ‘-mno-vis’.

-mvis2
-mno-vis2

With ‘-mvis2’, GCC generates code that takes advantage of version 2.0 of the UltraSPARC Visual Instruction Set extensions. The default is ‘-mvis2’ when targeting a cpu that supports such instructions, such as UltraSPARC-III and later. Setting ‘-mvis2’ also sets ‘-mvis’.

-mvis3
-mno-vis3

With ‘-mvis3’, GCC generates code that takes advantage of version 3.0 of the UltraSPARC Visual Instruction Set extensions. The default is ‘-mvis3’ when targeting a cpu that supports such instructions, such as niagara-3 and later. Setting ‘-mvis3’ also sets ‘-mvis2’ and ‘-mvis’.

-mcbcond
-mno-cbcond

With ‘-mcbcond’, GCC generates code that takes advantage of compare-and-branch instructions, as defined in the Sparc Architecture 2011. The default is ‘-mcbcond’ when targeting a cpu that supports such instructions, such as niagara-4 and later.

-mpopc
-mno-popc

With ‘-mpopc’, GCC generates code that takes advantage of the UltraSPARC population count instruction. The default is ‘-mpopc’ when targeting a cpu that supports such instructions, such as Niagara-2 and later.

-mfmaf
-mno-fmaf

With ‘-mfmaf’, GCC generates code that takes advantage of the UltraSPARC Fused Multiply-Add Floating-point extensions. The default is ‘-mfmaf’ when targeting a cpu that supports such instructions, such as Niagara-3 and later.

-mfix-at697f

Enable the documented workaround for the single erratum of the Atmel AT697F processor (which corresponds to erratum #13 of the AT697E processor).

These ‘-m’ options are supported in addition to the above on SPARC-V9 processors in 64-bit environments:

-m32
-m64

Generate code for a 32-bit or 64-bit environment. The 32-bit environment sets int, long and pointer to 32 bits. The 64-bit environment sets int to 32 bits and long and pointer to 64 bits.

-mcmodel=which

Set the code model to one of

medlow

The Medium/Low code model: 64-bit addresses, programs must be linked in the low 32 bits of memory. Programs can be statically or dynamically linked.

medmid

The Medium/Middle code model: 64-bit addresses, programs must be linked in the low 44 bits of memory, the text and data segments must be less than 2GB in size and the data segment must be located within 2GB of the text segment.

medany

The Medium/Anywhere code model: 64-bit addresses, programs may be linked anywhere in memory, the text and data segments must be less than 2GB in size and the data segment must be located within 2GB of the text segment.

embmedany

The Medium/Anywhere code model for embedded systems: 64-bit addresses, the text and data segments must be less than 2GB in size, both starting anywhere in memory (determined at link time). The global register %g4 points to the base of the data segment. Programs are statically linked and PIC is not supported.

-mmemory-model=mem-model

Set the memory model in force on the processor to one of

default

The default memory model for the processor and operating system.

rmo

Relaxed Memory Order

pso

Partial Store Order

tso

Total Store Order

sc

Sequential Consistency

These memory models are formally defined in Appendix D of the Sparc V9 architecture manual, as set in the processor’s PSTATE.MM field.

-mstack-bias
-mno-stack-bias

With ‘-mstack-bias’, GCC assumes that the stack pointer, and frame pointer if present, are offset by -2047 which must be added back when making stack frame references. This is the default in 64-bit mode. Otherwise, assume no such offset is present.


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